Sep 05, 2008
Next-Generation Intel Processor - Nehalem
by asdasdasd
Next-Generation Intel® Microarchitecture
Intel's next-generation microarchitecture (codenamed "Nehalem") represents the next step in processor energy efficiency, performance, and dynamic scalability. Designed from the ground up to take advantage of hafnium-based Intel® 45nm hi-k metal gate silicon technology, Nehalem will also be the first to introduce Intel® QuickPath technology.
Nehalem will be released in late 2008 for high-end desktop and dual-processor platforms and in Q3 2009 for mainstream desktop and mobile platforms. The microarchitecture is the planned successor to the Core microarchitecture.
Now performance really does come "on-demand"
We've expanded and redefined what's possible for technologies to come:
* Dynamic scalability, managed cores, threads, cache, interfaces, and power for energy-efficient performance on demand.
* Design and performance scalability for server, workstation, PC, and mobile demands with support for 2-8+ cores and up to 16+ threads with simultaneous multi-threading (SMT), and scalable cache sizes, system interconnects, and integrated memory controllers.
* Simultaneous multi-threading brings high-performance applications into mainstream computing with 1-16+ threads optimized for a new generation multi-core processor architecture.
* Scalable shared memory of Intel QuickPath technology features memory distributed to each processor with integrated memory controllers and high-speed point-to-point interconnects to unleash the performance of next-generation Intel® multi-core processors.
* Multi-level shared cache improves performance and efficiency by reducing latency to frequently used data.
Technology
Various sources have stated Nehalem's specification will have:
* Two, four, or eight cores
o 731 million transistors for the quad core variant
* 45 nm manufacturing process
* Integrated memory controller supporting DDR3 SDRAM and between one and six memory channels[citation needed]
* Integrated graphics processor (IGP) located off-die, but in the same CPU package
* A new point-to-point processor interconnect, the Intel QuickPath Interconnect, replacing the legacy front side bus
* Simultaneous multithreading, which enables two threads per core. Simultaneous multithreading has not been present on a consumer Intel processor since 2006 with the Pentium 4 and Pentium EE.
* Native (monolithic, i.e. all processor cores on a single die) quad- and octo-core (8) processors
* The following caches:
o 32 KB L1 instruction and 32 KB L1 data cache per core
o 256 KB L2 cache per core
o 2-3 MB L3 cache per core shared by all cores
* 33% more in-flight micro-ops than Conroe
* Second-level branch predictor and second-level Translation Lookaside Buffer
* Modular blocks of components such as cores that can be added and subtracted for varying market segments
Event demonstrations at the Shanghai Intel Developer Forum showed A1 silicon Bloomfield-based Nehalem processors at IDF running at 3.2 GHz. This processor had 32 KB L1 instruction and 32 KB L1 data cache, 256 KB L2 cache per core, and 8 MB of shared L3 cache.
Performance and power improvements
It has been reported that Nehalem will have a focus on performance, which accounts for the increased core size. Compared to Penryn, Nehalem will have:
* 1.1x to 1.25x the single-threaded performance or 1.2x to 2x the multithreaded performance at the same power level
* 30% lower power usage for the same performance
* According to a preview from AnandTech "expect a 20-30% overall advantage over Penryn with only a 10% increase in power usage. It looks like Intel is on track to delivering just that in Q4."
* Core-wise, clock-for-clock, Nehalem will provide a 15%-20% increase in performance compared to Penryn.
PC Watch found that a Nehalem "Gainestown" processor has 1.6x the SPECint_rate2006 integer performance and 2.4x the SPECfp_rate_2006 floating-point performance of a 3.0 GHz Xeon X5365 "Clovertown" quad-core processor.
A 2.93 GHz Nehalem "Bloomfield" system has been used to run a 3DMark Vantage benchmark and gave a CPU score of 17,966. The 2.66 GHz variant scores 16,294. A 2.4 GHz Core 2 Duo E6600 scores 4,300.
AnandTech tested the Intel QuickPath Interconnect (4.8 GT/s version) and found the copy bandwidth using triple-channel 1066 MHz DDR3 was 12.0 GB/s. A 3.0 GHz Core 2 Quad system using dual-channel 1066 MHz DDR3 achieved 6.9 GB/s.
Overclocking will be possible with Bloomfield processors and the X58 chipset. The Lynnfield and Havendale processors will use a PCH removing the need for a northbridge chipset.
Variants
Nehalem will come in variants for servers, desktops, and notebooks. The four-socket server CPU is codenamed Beckton, the two-socket server CPU is codenamed Gainestown, and the single-socket desktop CPU is codenamed Bloomfield. Server processors will support registered DDR3.
Seven code names have been associated with the Nehalem microarchitecture in a PC Watch article. These include two server processors, three desktop processors, and two mobile processors. The server processor, Beckton, will have 44 bits of physical memory address and 48 bits of virtual memory address. The mainstream and value processor, Havendale, will have a FDI bus. It has been said that Havendale will have two different IGP versions and at least six different parts, possibly six different frequencies.
Successor
Westmere (formerly Nehalem-C) is the name given to the 32nm shrink of Nehalem. Westmere should be ready for a 2009 release provided that Intel stays on target with its roadmap. However, it appears that the bulk of Westmere's versions, excluding mobile versions, will be released sometime in 2010. From various sources, Westmere's changes and improvements from Nehalem have been reported as follows:
- 32 nm process.
- Native six-core processors.
- The successor to Bloomfield and Gainestown is either quad-core or six-core.
- A new set of instructions that gives over 3x the encryption and decryption rate of AES processes compared to before.
- Delivers six new instructions that will be used by the Advanced Encryption Standard (AES) algorithm and also an instruction that will perform carry-less multiplication (PCLMULQDQ). Those instructions allow the processor to perform hardware accelerated encryption not only providing a faster execution but also protects against software targeted attacks.
- AES-NI may be included in the integrated graphics of Westmere.
- Westmere's integrated graphics may be released at the same time as the processor.
- Release dates:
- Q3 2009 for mobile chips.
- H1 2010 for high-end desktop chips (Bloomfield successor).
- H2 2010 for mainstream and value desktop chips, assuming Westmere is released for that segment.
The successor to Westmere will be Sandy Bridge, scheduled for release in 2010, according to Intel roadmaps.
Then, the successor to Sandy Bridge will be Haswell, scheduled for release in 2012. It will come with a new cache subsystem, a FMA (fused multiply-add) unit, and a vectorial coprocessor
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